When Bottlenecks Begin to Migrate - Repricing of Interconnect, HBM, and the Entire Storage Empire

Author: animajoe0917

On August 4, 2026, two significant events occurred in the storage industry.

In the morning, SK Hynix and SanDisk released the first standard specification for High Bandwidth Flash (HBF) at FMS 2026— a new storage tier positioned between HBM and SSD.

In the afternoon, TrendForce revealed that NVIDIA is evaluating a reduction in the HBM configuration for the Rubin Ultra, shifting from the originally planned 12hi HBM4E to a parallel evaluation of HBM4E 8hi, HBM4 12hi, and HBM4 8hi.

On the same day, Micron's stock rose by +3.68%, SK Hynix by +3%, and SanDisk by +4.42%.

Both events point in the same direction: the supply bottleneck of HBM is being addressed, and new alternatives are being formally proposed. However, this is not a story of "the storage bull market has arrived"; it is a story of the value distribution in storage being rewritten.

The key to this rewriting is not the advancement of NAND technology or breakthroughs in packaging technology— it is interconnect.

Conclusion in a nutshell

Interconnect (optical + electrical + packaging) is becoming the primary bottleneck in AI infrastructure, with HBM following closely behind. DDR, HBF, and CXL each have their positions, but their priorities decrease layer by layer. This is not a matter of one replacing the other, but rather a migration of the geographical location of bottlenecks— and the resulting revaluation of the entire storage system's value.

I. Core Proposition: Bottlenecks are Moving

At GTC 2026 in March, NVIDIA unveiled the Vera Rubin platform. Two numbers define the new paradigm:

• NVLink 6 single GPU bidirectional bandwidth of 3.6 TB/s, double that of Blackwell

• NVL72 total interconnect bandwidth of 260 TB/s, with 72 Rubin GPUs + 36 Vera CPUs fully connected

But what’s more interesting is not how much the bandwidth has increased, but who has increased it faster.

During the Blackwell era, the single card HBM3E bandwidth (8 TB/s) far exceeded NVLink 5 (1.8 TB/s), with the bottleneck in inter-chip communication. By the time of Vera Rubin, the HBM4 bandwidth doubled to about 1.2 TB/s per card, but NVLink 6 more than doubled. More critically— the cluster scale expanded from thousands of cards to hundreds of thousands, with the growth rate of inter-chip communication far outpacing the increase in single card memory bandwidth.

From "can one card be fed enough" to "can hundreds of thousands of cards communicate properly"— this is a structural migration.

Evidence Level: ★★★★★ (GTC 2026 official data)

II. Seven Points on the Same Logical Chain

Connecting the key events from March to August 2026—

March 2026 GTC: NVLink 6 = 3.6 TB/s, 260 TB/s total rack bandwidth

July 2026: NVIDIA Spectrum-X CPO shipment → CPO mass production two years ahead of schedule

July 2026: New Ease H1 +78-103%, 1.6T acceleration in Q3-Q4

July 2026: Intel EMIB-T released, MediaTek confirms dual route (EMIB-T + CoWoS)

August 2026: TSMC reverse-engineers EMIB, collaborates with Jingzhuo on EMIB-like packaging

August 2026: HBF standard released, UCIe directly connects CPU/GPU, Google enters the fray

August 2026: NVIDIA evaluates a reduction in HBM configuration

Each of these events is newsworthy on its own. Together, they represent seven facets of the same process:

• Interconnect bandwidth is accelerating (NVLink 6 → CPO shipment → 1.6T volume)

• Packaging is breaking monopolies (EMIB-T challenges CoWoS, TSMC is also developing EMIB-like solutions)

• HBM is being actively downgraded (the most financially robust buyers are cutting back)

• A new storage tier is emerging through interconnect buses (HBF + UCIe)

The name of the process is: the bottleneck is migrating from within the computing unit to the interconnect layer. Interconnect is not just the wiring between GPUs in a data center— it is becoming the hand that reorganizes the entire computing + storage pyramid.

III. Five-Layer Pyramid: Layer-by-Layer Breakdown

Layer 1: Optical-Electrical Interconnect --- Current Core Bottleneck ⭐⭐⭐⭐⭐

Why it’s crucial now: The physical limits of copper interconnect have been pushed to the extreme within the NVL72 rack, and the next generation NVL144/NVL288 must incorporate optical technology. The growth rate of interconnect bandwidth continues to outpace memory bandwidth growth— it’s not about "solving the bottleneck" but about continuing to expand the highway.

|---------------------------|-----------------------------|-----------------| | Metric | Value | Source | | NVLink 6 single card bidirectional bandwidth | 3.6 TB/s | NVIDIA GTC 2026 | | NVL72 total rack interconnect bandwidth | 260 TB/s | NVIDIA Official | | NVIDIA Spectrum-X CPO | 400 Tb/s, already shipped | TrendForce | | Broadcom 51.2T Bailly CPO | Continuous small shipments | TrendForce | | CPO/NPO market 2030E | $390B+ | TrendForce | | New Ease H1 2026 net profit | 7-8 billion RMB, +78-103% YoY | Company Announcement | | Zhongji Xuchuang Q1 2026 revenue | 19.5 billion RMB, +192% YoY | Company Announcement | | Tianfu Communication H1 2026 net profit | 1.12-1.3 billion RMB, +25-45% YoY | Company Announcement | | 1.6T optical module volume node | Acceleration in Q3-Q4 2026 | New Ease conference call | | Silicon photonics proportion | "Significantly increased", annual shipment proportion surged | New Ease conference call | | Zhongji Xuchuang Hong Kong IPO | 55 billion HKD (~$70B), preparing for 3.2T + silicon photonics | HKEX Announcement | | Hyperscale cloud AI CapEx 2026E | $700B+ | CoBank |

Interconnect is the only track that meets all three conditions:

• Fastest growth (1.6T volume + silicon photonics ramp-up + CPO from 0 to 1)

• Most robust structure (the physical migration from copper to optical is a one-way street)

• Largest selection space (optical modules, optical engines, silicon photonics, DSPs, switching chips, lasers— the industry chain is deep enough)

Risks: Valuation (Zhongji Xuchuang PE 81x TT P/E), silicon photonics physical limits, CapEx growth rate inflection point.

Evidence Level: ★★★★★

Layer 2: Advanced Packaging --- The Physical Foundation of Interconnect ⭐⭐⭐⭐☆

Why it’s important now: The ultimate constraint on interconnect bandwidth lies not in cables or fibers, but in the physical wiring between chips. When the supply ceiling for packaging opens, it directly determines the speed of CPO + Chiplet hybrid packaging implementation.

TSMC's CoWoS capacity is extremely tight. On July 30, The Information reported that TSMC is collaborating with Jingzhuo Technology to develop an "EMIB-like" packaging solution— because the CoWoS silicon interposer solution is too costly and lacks capacity in large-scale Chiplet scenarios. TSMC's reverse engineering of Intel's EMIB technology route indicates that the bottleneck of CoWoS has become severe enough to necessitate alternative paths.

Intel's EMIB-T is making progress. At IEEE ECTC 2026, Intel showcased EMIB-T— introducing TSV for vertical power supply in silicon bridges. According to supply chain sources, EMIB-T costs 50% less than CoWoS, with a yield of 98%, and is expected to enter mass production in 2027. MediaTek confirmed in its Q2 earnings report that its AI ASIC project is using both EMIB-T and CoWoS simultaneously. More critically— Intel's 18A has secured customers including AMD, NVIDIA, Marvell, Microsoft, Micron, and OpenAI, with a yield of 85%.

|------|---------------------------------|--------------------------| | Dimension | Intel | TSMC | | Advanced Process | 18A yield 85%, High NA EUV debut | 3nm monthly production of 180,000 wafers (Q4E), 2nm in progress | | Packaging Solution | EMIB-T: 50% lower cost, 98% yield | CoWoS: mature but capacity tight, developing EMIB-like solutions | | Customer Progress | AMD/NVIDIA/Marvell/Microsoft/Micron/OpenAI | Absolute dominance, significant packaging capacity bottleneck |

Investment Implications: Packaging has shifted from a single supplier to a dual supplier model → packaging capacity no longer constrains interconnect → CPO + Chiplet hybrid packaging can be implemented more quickly → interconnect demand catalyzed in the second order. The packaging chain does not directly buy interconnect targets, but it determines when the supply ceiling for interconnect will open.

Evidence Level: ★★★★☆

Layer 3: HBM --- A Priced Bottleneck, Basic and Loosening ⭐⭐⭐⭐

Why It Matters Now:

HBM remains the "close memory" for AI GPUs, with the nearest physical location and highest bandwidth. However, supply constraints have shifted from short-term bottlenecks to structural constraints—where the marginal cost of increasing HBM capacity begins to exceed the marginal benefits.

The three oligopolists (Samsung with approximately 39% market share, SK Hynix, and Micron) have a clear roadmap: HBM3E → HBM4 → HBM4E. BofA predicts the market will grow from about $350 billion in 2026 to $2.46 trillion by 2030 (approximately sevenfold).

However, a TrendForce report on August 4 revealed a key turning point:

Starting Q3 2026, Nvidia will change the HBM configuration of the Rubin Ultra from 12hi HBM4E to parallel evaluations of HBM4E 8hi, HBM4 12hi, and HBM4 8hi. It’s not just Nvidia; several CSPs are also considering reducing the HBM capacity of their self-developed ASICs.

The reason: DRAM shortages are expected to continue until 2027, and there is uncertainty regarding the validation progress of HBM4E 12hi. When even the most financially robust buyers are actively downgrading configurations, what does that signify?

The supply constraints of HBM have transitioned from short-term bottlenecks to structural constraints.

HBM remains irreplaceable (inference batch=1 is latency-sensitive, and HBM bandwidth remains the primary constraint), but from an investment perspective:

• The growth model is a linear improvement (stacking layers, TSV density), not an architectural-level reconstruction.
• The oligopolistic structure is already fully priced in.
• When Nvidia is cutting configurations and HBF is releasing standards next door—HBM's scarcity is being squeezed from both sides.

→ There is configuration value, but no excess elasticity.

Evidence Level: ★★★★★

Layer 4: HBF --- A Whole New Thing, 0→1 ⭐★★★☆

Why It Matters Now:

It is not meant to replace HBM. It aims to fill a gap created by HBM's high prices and low capacities. The "memory wall" of the inference era is fundamentally a capacity wall rather than a bandwidth wall.

The HBF first standard released on August 4 needs to be carefully dissected.

|----|---------------------------------------------| | Dimension | HBF | | Capacity | 8-layer/16-layer NAND stacking, up to 512GB | | Bandwidth | 3 levels: 0.4 - 3.0 TB/s | | Interface | UCIe (Universal Chiplet Interconnect Express) | | Positioning | A new storage tier between HBM and SSD | | Alliance | SK Hynix + SanDisk, OCP release, specifications in 6 months | | Ecosystem | Google + Tenstorrent have joined, Google DeepMind roundtable on 8/6 |

The logic of HBF: using NAND stacking for high bandwidth, tightly coupled to CPU/GPU via UCIe interconnect bus. HBM single stack capacity is 24-36 GB, while HBF is 512GB—an order of magnitude difference. HBM bandwidth is 1.2-2 TB/s, while HBF Grade 3 is 3.0 TB/s—higher than HBM4.

It is not meant to replace HBM. It aims to fill a gap created by HBM's high prices and low capacities.

The "memory wall" of the inference era is fundamentally a capacity wall rather than a bandwidth wall—KV Cache often requires tens to hundreds of GB, necessitating a large near-compute storage pool, not HBM's 8 TB/s maximum bandwidth. HBF uses NAND for high bandwidth, costing a fraction of HBM, with more reads than writes and prefetch capabilities. Google DeepMind's involvement is not just for show—they are the first to hit this wall with their own inference infrastructure.

Core Significance for Framework:

The existence of HBF is not based on breakthroughs in NAND technology, but on breakthroughs in interconnect bus bandwidth. UCIe marks the penetration of interconnect architecture from rack-level to chip-level. Without UCIe, there would be no HBF—it validates the ability of interconnects to redefine storage value.

Evidence Level: ★★★☆ (OCP formal standards + alliance established, but mass production is at least 2 years away)

Beneficiaries of HBF:

• SanDisk ($SNDK): One of the dual protagonists in the HBF alliance, stock price has risen 4600% after split, with a gross margin of 78.4%—the market is not pricing NAND, but pricing "NAND redefined as an AI platform component."
• SK Hynix: Dual lines of NAND + HBM.
• Micron ($MU): Benefiting across the storage spectrum.
• Domestic mapping: Yangtze Memory (NAND), Chipone/Lanqi (UCIe/Chiplet), but HBF packaging stacking requirements are extremely high, making it difficult to enter the core chain in the short term.

Layer 5: CXL Memory Pool --- Long-term Options for Interconnect Logic ⭐⭐⭐

Why It’s Only Suitable for Tracking Now:

CXL is not essentially about "more memory"; it’s about pooling memory by extracting it from servers through interconnect buses— a natural extension of interconnect logic.

Latest Developments:

• Lanqi Technology is the first globally to trial produce CXL 3.2 MXC chips (64GT/s), integrating into Samsung/SK Hynix supply chains—Chinese controller chips have entered Korean manufacturers for the first time.
• Meta is recycling old DDR4 using CXL, reducing server costs by 25%.
• Marvell has launched the Tanzanite integrated end-to-end CXL platform.

The logic is correct, but the ecosystem is not mature enough. CXL-aware OS/memory orchestration/application adaptation is still in its early stages, and true large-scale deployment is expected by 2027-2028. It is suitable for tracking pools, but not for placing orders at current prices.

Evidence Level: ★★★ (Industry data is sufficient, but lacks observable revenue inflection points)

Below: DDR5 ⭐⭐⭐ / NAND ⭐⭐☆

DDR5 naturally increases with the number of host CPU cores in AI servers, without independent excess catalysts. NAND operates on independent cyclical logic; training does not rely on storage bandwidth, while inference has incremental capacity demands rather than performance bottlenecks.

There is configuration value, but it is not prioritized within the "bottleneck migration" framework.

IV. Investment Mapping

|---------|---------|-------------------------------------------------|------------------|----------------------| | Level | Priority | Representative Targets | Logic Type | Time Window | | Optoelectronic Interconnect | ★★★★★ | Zhongji Xuchuang/Xinyi Sheng/Tianfu/$COHR/$LITE/$AAOI/$MRVL/$AVGO/$SIVE | Direct beneficiaries of bottlenecks, architectural reconstruction | 2026H2--2027 volume main rise | | Advanced Packaging | ★★★★☆ | Intel/TSMC/packaging equipment chain | Interconnect foundation, breaking CoWoS monopoly | 2026--2027 capacity release | | HBM | ★★★★ | SK Hynix/Samsung/Micron | Basic plate, supply constraints continue | Ongoing, but elasticity converges | | HBF (new) | ★★★☆ | SanDisk/SK Hynix/$MU | A brand new category 0→1, OCP standardization | 2026--27 narrative, 2028+ performance | | CXL Memory Pool | ★★★ (long-term) | Lanqi Technology/$MRVL | Extension of interconnect logic, observation pool | 2027--2028 observation | | DDR5 | ★★★ | Samsung/SK Hynix/Micron | Volume increase logic | With server shipments | | NAND | ★★☆ | Samsung/Kioxia/Yangtze Memory | Independent track | Cyclical logic |

Marvell ($MRVL) deserves special mention. It spans DSP + Teralynx switching chips + custom ASIC + CXL, being a full-stack supplier of interconnect infrastructure. Teralynx 10 (3nm, 100.4 Tb/s) and custom ASICs have not yet been fully priced by the market—if interconnect is the primary storyline, Marvell's configuration value is comparable to that of optical modules themselves.

V. Risk Warning

• HBF is a standard, not a product: It may not achieve scale shipments until 2028, and from 2026-2027, it will mainly rely on narrative-driven growth, not performance validation. The valuation of SanDisk's 4600% increase + 78.4% gross margin needs continuous verification.
• AI CapEx cycle inflection point: If CapEx growth drops from $700B+ in 2027, both interconnect and HBM growth rates will be pressured.
• Technical route risks: Silicon photonic modulators are approaching physical limits, and next-generation optical modulation technologies (thin-film lithium niobate/polymer) are still immature.
• Valuation risks: Zhongji Xuchuang PE 81x, Xinyi Sheng PE 65x, current valuations imply continued unexpected volume growth. Once 1.6T ramps up or silicon photonic progress falls short of expectations, elasticity will quickly converge.
• Geopolitical risks: If export controls on optical modules/engines escalate, A-share targets (Zhongji Xuchuang, Xinyi Sheng, Tianfu) will be the first to be affected; US stock targets ($COHR, $LITE, $AAOI, $MRVL, $AVGO) are relatively more diversified.

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